The present invention relates in general to digital logic test equipment and more particularly to a method and apparatus for inputting data for adjustment of test signal timing relationships.
To test a digital circuit it is often useful to apply several digital test signals to a number of points in the circuit, each test signal changing state in a specified sequence and at a specified time with respect to a reference clock cycle. In the prior art, signal pattern generators capable of providing these timed test signal patterns were preprogrammed to provide the proper signal patterns and timing by an operator inputting numerical pattern and timing data. Usually digital circuit manufacturers provide test signal timing data graphically in the form of timing diagrams. Therefore, prior to programming a signal pattern generator to reproduce the test signals, an operator must first convert the graphical timing data of the timing diagrams into numerical timing data and then input that numerical data into the pattern generator. This conversion process takes time and is subject to error.